m .tec TBS6416B4E revision_1.1 1 sep. 2000 1m x 16bit x 4 banks synchronous dram general description the TBS6416B4E is 67,108,864 bits synchronous high data rate dynamic ram organized as 4 x 1,048,576 words by 16 bits, fabricated with m?tec high performance cmos technology. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. features jedec standard 3.3v power supply lvttl compatible with multiplexed address four-banks operation mrs cycle with address key programs -. cas latency (2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) all inputs are sampled at the positive going edge of the system clock. burst read single-bit write operation dqm for masking auto & self refresh 64ms refresh period (4k cycle) ordering information part no. max freq. interface package TBS6416B4E-7g 143mhz lvttl 54 tsop(ii) .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 2 sep. 2000 pin configuration (top view) 54pin tsop (ii) (400mil x 875mil) (0.8 mm pin pitch) .com .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 3 sep. 2000 pin function description pin name function description a0~ a11 address multiplexed pins for row and column address row address: a0~ a11. column address: a0 ~ a7. bs0, bs1 bank select bank to activate during row address latch time, or bank to read/write during address latch time. dq0 ~dq15 data input / output multiplexed pins for data output and input. /cs chip select disable or enable the command decoder. w hen command decoder is disabled, new command is ignored and previous operation continues. /ras row address strobe command input. when sampled at the rising edge of the clock, /ras, /cas and /we define the operation to be executed. /cas column address strobe referred to /ras /we write enable referred to /ras udqm/ldqm input /output mask the output buffer is placed at hi-z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. clk clock input system clock used to sample inputs on the rising edge of clock. cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. vcc power (+3.3 v) power for input buffers and logic circuit inside dram. vss ground ground for input buffers and logic circuit inside dram. vcc q power (+ 3.3 v) for i/o buffer separated power from vcc , used for output buffers to improve noise. vss q ground for i/o buffer separated ground from vss , used for output buffers to improve noise. nc no connection no connection .com .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 4 sep. 2000 functional block diagram bank select data input row decoder & refresh counter column buffer 1mx16 1mx16 1mx16 1mx16 sense amp column decoder output buffer dq latency & burst length programming register address buffer add commend decoder & clock buffer /cs / ras / cas / we clk cke .com .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 5 sep. 2000 absolute maximum rating parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on vcc supply relative to v ss vcc, vcc q -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 power dissipation p d 1 w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the recommended operating conditions. exposure to higher voltage than recommended for extended periods of time could affect device reliability. dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70c) parameter symbol min typ max unit note supply voltage vcc, vcc q 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 vcc q +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh =-2ma output logic low voltage v ol - - 0.4 v i ol =2ma input leakage current (input) i il -1 - 1 ua 3 input leakage current (i/o pins) i il -1.5 - 1.5 ua 3,4 notes: 1. v ih (max) = 5.6v ac. the overshoot voltage duration is Q 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is Q 3ns. 3. any input 0v Q v in Q vcc q, input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. d out is disabled, 0v Q v out Q vcc q .com .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 6 sep. 2000 dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70c) parameter symbol test condition TBS6416B4E-7g unit note operating current (one bank active) i cc1 burst length = 1 t rc R t rc (min) iol = 0ma 100 ma 1 i cc2 p cke Q v il (max), t cc = 15 ns 2 pre-charge standby current in power- down mode i cc2 ps cke&clk Q v il (max), t cc = 2 ma i cc2 n cke R v ih (min), /cs R v ih (min) , t cc = 15ns input signals are stable 30 pre-charge standby current in non power-down mode i cc2 ns cke R v ih (min), clk Q v il (max) , t cc = input signals are stable 10 ma i cc3 p cke Q v il (max), t cc = 15 ns 5 active standby current in power-down mode i cc3 ps cke&clk Q v il (max), t cc = 5 ma i cc3 n cke R v ih (min), /cs R v ih (min) , t cc = 15ns input signals are stable 40 active standby current in non power-down mode (one bank active) i cc3 ns cke R v ih (min), clk Q v il (max) , t cc = input signals are stable 20 ma cl = 3 150 operating current (burst mode) i cc4 i ol =0 ma page burst 2banks activated t ccd = 2clk s cl = 2 140 ma 1 refresh current i cc5 t rc R t rc (min) 160 ma 2 self refresh current i cc6 cke Q 0.2v 1 ma note: 1.measured with outputs open. 2.refresh period is 64 ms. .com .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 7 sep. 2000 ac characteristics and operating condition for pc-143 (vcc=3.3v0.3v, ta=0 to 70c) TBS6416B4E-7g parameter symbol min max unit row active to row active delay t rrd 14 ns /ras to /cas delay t rcd 20 ns row pre-charge time t rp 20 ns row active time t ras 45 100k ns row cycle time t rc 63 ns col. address to col. address delay t ccd 1 clk write recovery time t wr 14 ns cl=2 10 1000 clk cycle time t ck cl=3 7 1000 ns clk high level width t ch 2.5 ns clk low level width t cl 2.5 ns cl=2 6 access time from clk t ac cl=3 5.4 ns output data hold time t oh 2.5 ns data-in set-up time t ds 1.5 ns data-in hold time t dh 1 ns address set-up time t as 1.5 ns address hold time t ah 1 ns cke set-up time t cks 1.5 ns cke hold time t ckh 1 ns command set-up time t cms 1.5 ns command hold time t cmh 1 ns refresh time t ref 64 ms mode register set cycle time t rsc 15 ns .com .com .com .com 4 .com u datasheet
m .tec TBS6416B4E revision_1.1 8 sep. 2000 54pin plastic tsop(ii) (400mil) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. a 22.62 max. 0.891 max. b 0.91 max. 0.036 max. j 0.800.20 0.031 +0.009 ?0.008 k 0.145 0.0060.001 l 0.500.10 0.020 +0.004 ?0.005 m 0.13 0.005 n 0.10 0.004 +0.025 ?0.015 c 0.80 (t.p.) 0.031 (t.p.) d 0.32 0.0130.003 e 0.100.05 0.0040.002 f 1.20 max. 0.048 max. g 1.00 0.039 h 11.760.20 0.4630.008 i 10.160.10 0.4000.004 p3 +0.08 ?0.07 +7 ?3 3 +7 ?3 m 54 28 12 7 p a g cn b m d l k j h i e f detail of lead end .com .com .com 4 .com u datasheet
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